1. Field of the Invention
This invention relates generally to nonvolatile memory devices, circuits, systems, and methods of operation. More particularly, this invention relates to floating gate tunnel oxide (FLOTOX) Electrical Erasable Programmable Read Only Memory (EEPROM) devices, circuits, systems, and methods of operation.
2. Description of Related Art
Nonvolatile memory is well known in the art. The different types of nonvolatile memory that employ a charge retention mechanism include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. The charge retention mechanism may be charge storage, as in a floating gate memory cell, and charge trapping, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memory cell
A NAND Flash memory is formed of strings of serially connected charge retaining transistors with contact metallurgy between the memory cells to save silicon area. Since NAND Flash memory cell does not require any contact metallurgy in the drain and source terminals of the charge retaining transistors, the single cell size is the smallest of the nonvolatile memory circuits.
The NAND Flash memory cell design has several advantages. Firstly, its cell size is highly scalable and is able to have a cell size that is a factor of approximately four times (4×) larger than the minimum feature size (λ2) of the manufacturing technology. This has held in technologies with feature sizes from 0.25 μm down to 20 nm. This is the smallest nonvolatile memory cell when compared to other nonvolatile cell types. Secondly, NAND Flash memory cell design uses a low-current Fowler-Nordheim tunneling phenomena for both program and erase operations. The Fowler-Nordheim Tunneling allows the program and erase operations to be performed in relatively larger memory unit sizes and a faster speed. The Fowler-Nordheim erase operation is typically performed in a unit of a large sector with sizes ranging from 512 Kb to 2 Mb and 1 mS fast erase time in current specifications. The Fowler-Nordheim program is performed in a unit of a large page size varying from 512 B to 2 KB with a fast speed of 200 μS typically in the current specifications.
The only disadvantage of NAND Flash memory array is the read operation that can only be performed in serial mode with a slow speed of 10 μs per page. The NAND Flash memory array is commonly and extensively used as a slow, serial data storage memory for audio and video applications. A NAND Flash memory array is not suitable for code storage in embedded MCU applications. The highest density of a NAND Flash memory device at the current lithographic minimum feature size of 20 nm for current manufacturing technology is 64 Gb (bits).
By contrast, NOR Flash memory device is formed of an array of less-compact charge retaining transistors that are fundamentally connected in parallel, rather than serially in a NAND Flash memory array. Like a NAND Flash memory charge storage transistor, the NOR Flash memory charge storage transistor is also made of the stack-gate cell structure for the floating gate transistors. In the charge retaining transistors, the NOR Flash memory charge trapping transistors are essentially identical to the NAND Flash memory charge trapping transistors. Each NOR Flash memory cell has a contact metallurgy at each drain and source node to connect each NOR Flash memory cell to the common bit lines and source lines. The cell size for the NOR Flash memory, therefore, is larger than the NAND Flash memory.
A disadvantage of the NOR Flash memory cell is that dimensions of the cell are not as highly scalable as NAND Flash memory cell counterpart. In current manufacturing technology, the NOR Flash memory cell technology is approximately three generations behind that of the NAND Flash memory cell technology. The nominal cell size at the manufacturing technology at 65 nm. The relative cell size as compared to the smallest feature size possible with the current manufacturing technology is getting large as the manufacturing technology migrates below 65 nm. In the manufacturing technology process nodes of 45 nm and below, the one-transistor NOR Flash memory cell is realized with an area of 15 times the minimum feature size (λ2).
A second disadvantage of a NOR Flash memory cell is the usage of the high-current channel-hot electron (CHE) phenomena for programming. On the average, each NOR flash memory cell has a high cell current of more than 100 uA for a period of 5 μS flowing through it for program operation. As a result, the NOR flash memory program operation can only be performed in units of byte or word when an on-chip weak high voltage charge-pump circuit is employed rather than an external programming power supply voltage source (VPP). The programming speed of the NOR flash memory array is for a page size of 512 B or 2 KB and is much slower than NAND flash memory array and EEPROM memory array in roughly equivalent array densities that use a low-current Fowler-Nordheim phenomena.
A third disadvantage of a NOR Flash memory cell is the long erase time due to the long-held concern for over-erase. Although a one-transistor NOR flash memory cells employs similar low-current Fowler-Nordheim scheme like NAND and EEPROM for its erase operation, the organization of one-transistor cell array is connected in parallel-form and is prone to a high cell leakage current as a result of the erase operation. The NOR Flash memory array erase is performed in a large unit of a block with a size ranging from 512 Kb to 2 Mb.
The only advantage of NOR Flash memory array is that its read operation. The NOR Flash memory is read randomly with a fast speed of 100 ns or below in a unit of byte or word in an array density of approximately 1 Gb. The NOR Flash memory array read speed is approximately 200 faster than the read speed of its NAND flash memory array counterpart. As a result, a NOR flash memory array is commonly and extensively used as a fast random code storage memory for embedded MCU applications. The current NOR Flash memory array technology has migrated to a minimum feature size of 45 nm for mass production and the highest density achieved is up to 2 Gb in a single chip.
As is known in the art, an EEPROM memory array is structured to be a byte-wise erasable structure as compared to block-wise erasable NAND flash memory arrays. EEPROM memory array require more die area than a NAND flash memory of the same capacity because each EEPROM memory cell requires a read, write and erase transistor. Conversely, in a NAND flash memory array, the erase circuits are shared by large blocks of cells (often 512×8 bits).
An EEPROM memory array design has its own set of advantages and disadvantages. The first disadvantage is a large cell size that is the largest among the nonvolatile memory structures. Currently, the EEPROM manufacturing technology process, in real production, is about four (4) generations behind NOR Flash memory manufacturing technology and seven (7) generations behind the NAND Flash memory manufacturing technology. The cell size will be relatively larger as technology migrates below 0.15 μm. In the manufacturing process node above and including 0.18 μm, the EEPROM cell has been realized with a cell area size of about 90 times the minimum feature size (λ2) but will have an area larger than 100 times the minimum feature size (λ2) when migrating below 0.15 μm.
The second disadvantage of the EEPROM memory array design is that a very high programming voltage is required. The programming voltage is as high as 16V in the cell channel region between its drain and source nodes for performing proper Fowler-Nordheim Program operation. As a result, the EEPROM memory array program operation is the most critical one as compared to NAND Flash memory array and NOR Flash memory array. The very high programming voltage requirement in cell's channel region between the drain and source prevents the EEPROM memory cell area from further scaling below the 0.15 μm minimum feature size. During a page program operation, almost 1K bit lines and one word line is charged to the very high programming voltage of 16V in the worst-case. The page size varies from 8 bytes in low-density 2 kb part to 256 Bytes for high-density parts such as 1-2 Mb with page program speed of around 1 mS.
The first advantage of EEPROM memory array design is the short program time which is attributed to two major advantages. As opposed to the conventional NOR Flash design, the threshold voltage (Vt) of EEPROM memory cells is decreased after program and is increased after erase. Therefore the concern of over-erase in a one-transistor NOR Flash memory array is not a concern in a two-transistor EEPROM array design. The EEPROM memory cell has a two-transistor structure with a single polycrystalline silicon bit line select transistor connected in series with a charge retaining transistor (floating-gate or SONOS) double polycrystalline silicon storage cell. The threshold voltage (Vt) of the bit line select transistor is a positive voltage level of 0.7V. The effective threshold voltage (Vt) of the two-transistor EEPROM memory cell is a positive voltage level of approximately 0.7V even the charge retaining transistor threshold voltage level (Vt) becomes negative after over-program operation. As a result, the two-transistor EEPROM memory cell has no concern for over-programming of the charge retaining transistor. Thus the program operation is fast in unit of page with a speed of about 1 mS in the two-transistor EEPROM memory cell.
The second advantage of the two-transistor EEPROM memory array design is the number of Program and Erase (P/E) endurance cycles that the two-transistor EEPROM memory array is able to endure. Currently the two-transistor EEPROM memory array can endure at least 1 million program and erase cycle in units of byte or page. Therefore, the two-transistor EEPROM memory array is the best nonvolatile storage memory for those extremely high-frequency changing rate of byte-alterable or page-alterable data applications.
The third advantage of the EEPROM memory array is the fast random read operation. The read operation of the EEPROM memory array is as fast as the read operation of NOR Flash memory array. The EEPROM memory array read operation can be performed in a random mode similar to that of the NOR memory array and an SRAM memory array with a fast read speed of 100 ns or below in units of bytes or words in the widest operating ranges of the power supply voltage source (i.e. 1.8V to 5.5V). Currently, the EEPROM memory array technology has migrated to a manufacturing process having a feature size of 0.15 nm in mass production and has achieved the highest density up to 2 Mb in a single chip.
The cell threshold voltages of the three nonvolatile memories are optimally defined differently for different cell array architectures, different program and erase physics schemes, and different applications in market. For example, the preferred threshold voltage of NAND Flash memory cell operation decreases after erase and is commonly set to a voltage level of approximately −2.0V and the program threshold voltage is increased to a positive threshold voltage level of approximately +2.0V. The NAND Flash memory cell has a negative threshold voltage because the array is constructed of multiple NAND cell strings with each string having one additional bit line select transistor connected to an associated bit line at the top of the NAND cell string. A source select transistor is located at the bottom of the NAND cell string and is connected to an associated source line. The bit line and source line transistors have a positive threshold value of approximately 0.7V. There is no leakage current due to the negative-threshold voltage of the NAND cells can occur in the unselected NAND strings when a voltage level of approximately 0.0V is coupled to one of gates of the bit line and source line transistors.
Like the NAND Flash memory array, a FLOTOX-based EEPROM memory cell is virtually a two-transistor cell structure with one bit line select transistor on top with a threshold voltage set to a positive voltage level of approximately 0.7V in series with one bottom charge retention transistor with two threshold voltage levels representing the logic level of the data states. The threshold voltage level for an erase operation is approximately +2.0V and the threshold voltage level for a program operation is approximately −2.0V. There is no concern for bit line leakage because of the negative threshold voltage level of the charge retaining transistors of each two-transistor EEPROM memory cell because of the bit line select transistor preventing the leakage.
Unlike the NAND Flash memory cell or the EEPROM memory cell, the NOR Flash memory cell is virtually a one-transistor memory cell structure without a bit line or source line select transistor. As a result, the two threshold voltage levels of the NOR Flash memory cell are tuned positive to prevent the false reading due to the negative voltage level threshold voltage induced leakage in the bit lines of the array. The erase threshold voltage level is a lower positive threshold voltage level and is usually defined to be somewhat greater than +2.0V, for avoiding over-erase issue. The program threshold voltage level is high positive threshold voltage level and is defined to be greater than 3.5V.
Typically, the three types of nonvolatile memory structures are targeted three different storage markets and technologies are not compatible. The NAND Flash memory has been extensively used as a slow-serial-read, extreme-high-density, block-alterable memory array for huge data storage. Conversely, the NOR Flash memory is used as a fast-random-read medium-high-density, sector-alterable memory array for program code storage. Unlike the NAND and NOR Flash memories, the EEPROM memory is broadly used as a fast-random-read, byte-alterable memory array for small data storage.
In the past years, the market for nonvolatile memory has strongly demanded a low-cost hybrid storage solution that allows code and data to be integrated on a same die. In the prior art, there have been claims for ultimate universal combinations of nonvolatile memory design. Most of the designs were based on Flash NAND and NOR technology that has a wide variety in cell structures, program and erase schemes, and manufacturing processes. None of the prior is based on the mainstream two-transistor FLOTOX EEPROM memory technology. As a result, the Flash based combination structures are unable to meet EEPROM memory array reliability requirements of 1 million program/erase cycles in units of byte for 10-year product cycle. The Flash-based combination nonvolatile memory chips are able to meet the reliability criteria of the EEPROM memory now and for-seeable future. In other words, those Flash-based combination memories of the prior art are more focused for a Block-alterable, code-oriented design, rather than a byte-alterable data-oriented solution. There is a need in the market for a byte-alterable and data oriented combination of NAND, NOR, and EEPROM integrated on to one semiconductor substrate die.